using System;
using System.Diagnostics;
namespace Unity.Burst.Intrinsics
{
public unsafe static partial class Arm
{
///
/// Neon intrinsics
///
public unsafe partial class Neon
{
///
/// Evaluates to true at compile time if Armv8.2 extension feature intrinsics are supported. These include DotProd, Crypto, RDMA, so the property is equivalent to (IsNeonCryptoSupported && IsNeonDotProdSupported && IsNeonRDMASupported)
///
public static bool IsNeonArmv82FeaturesSupported { get { return false; } }
/// Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADD Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vadd_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADD Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADD Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vaddd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADD Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vaddd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SADDL instruction extracts each source vector from the lower half of each source register, while the SADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UADDL instruction extracts each source vector from the lower half of each source register, while the UADDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddl_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDW2 Vd.8H,Vn.8H,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDW2 Vd.4S,Vn.4S,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.The SADDW instruction extracts the second source vector from the lower half of the second source register, while the SADDW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDW2 Vd.2D,Vn.2D,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDW2 Vd.8H,Vn.8H,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDW2 Vd.4S,Vn.4S,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDW2 Vd.2D,Vn.2D,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddw_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQADD Bd,Bn,Bm
/// SByte a0
/// SByte a1
/// SByte
[DebuggerStepThrough]
public static SByte vqaddb_s8(SByte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQADD Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqaddh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQADD Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqadds_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQADD Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqaddd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQADD Bd,Bn,Bm
/// Byte a0
/// Byte a1
/// Byte
[DebuggerStepThrough]
public static Byte vqaddb_u8(Byte a0, Byte a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQADD Hd,Hn,Hm
/// UInt16 a0
/// UInt16 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqaddh_u16(UInt16 a0, UInt16 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQADD Sd,Sn,Sm
/// UInt32 a0
/// UInt32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqadds_u32(UInt32 a0, UInt32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQADD Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqaddd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.8B,Vn.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuqadd_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.16B,Vn.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuqaddq_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.4H,Vn.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuqadd_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.8H,Vn.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuqaddq_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuqadd_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuqaddq_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Dd,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuqadd_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuqaddq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Bd,Bn
/// SByte a0
/// Byte a1
/// SByte
[DebuggerStepThrough]
public static SByte vuqaddb_s8(SByte a0, Byte a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Hd,Hn
/// Int16 a0
/// UInt16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vuqaddh_s16(Int16 a0, UInt16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Sd,Sn
/// Int32 a0
/// UInt32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vuqadds_s32(Int32 a0, UInt32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUQADD Dd,Dn
/// Int64 a0
/// UInt64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vuqaddd_s64(Int64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.8B,Vn.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqadd_u8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.16B,Vn.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqaddq_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.4H,Vn.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqadd_u16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.8H,Vn.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqaddq_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqadd_u32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqaddq_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Dd,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqadd_u64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqaddq_u64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Bd,Bn
/// Byte a0
/// SByte a1
/// Byte
[DebuggerStepThrough]
public static Byte vsqaddb_u8(Byte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Hd,Hn
/// UInt16 a0
/// Int16 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vsqaddh_u16(UInt16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Sd,Sn
/// UInt32 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vsqadds_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USQADD Dd,Dn
/// UInt64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vsqaddd_u64(UInt64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_s16(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_s32(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_s64(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_u16(v64 a0, v128 a1, v128 a2)
{
return vaddhn_high_s16(a0, a1, a2);
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_u32(v64 a0, v128 a1, v128 a2)
{
return vaddhn_high_s32(a0, a1, a2);
}
/// Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are truncated. For rounded results, see RADDHN.The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vaddhn_high_u64(v64 a0, v128 a1, v128 a2)
{
return vaddhn_high_s64(a0, a1, a2);
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_s16(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_s32(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_s64(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_u16(v64 a0, v128 a1, v128 a2)
{
return vraddhn_high_s16(a0, a1, a2);
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_u32(v64 a0, v128 a1, v128 a2)
{
return vraddhn_high_s32(a0, a1, a2);
}
/// Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see ADDHN.The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RADDHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vraddhn_high_u64(v64 a0, v128 a1, v128 a2)
{
return vraddhn_high_s64(a0, a1, a2);
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Sd,Sn,Sm
/// Single a0
/// Single a1
/// Single
[DebuggerStepThrough]
public static Single vmulxs_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Dm
/// Double a0
/// Double a1
/// Double
[DebuggerStepThrough]
public static Double vmulxd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_lane_f32(v64 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_lane_f32(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_lane_f64(v64 a0, v64 a1, Int32 a2)
{
return vmulx_f64(a0, a1);
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_lane_f64(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]
/// Single a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Single
[DebuggerStepThrough]
public static Single vmulxs_lane_f32(Single a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
/// Double a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
public static Double vmulxd_lane_f64(Double a0, v64 a1, Int32 a2)
{
return vmulxd_f64(a0, a1.Double0);
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_laneq_f32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_laneq_f32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmulx_laneq_f64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulxq_laneq_f64(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Sd,Sn,Vm.S[lane]
/// Single a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Single
[DebuggerStepThrough]
public static Single vmulxs_laneq_f32(Single a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]
/// Double a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vmulxd_laneq_f64(Double a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FDIV Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdiv_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FDIV Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdivq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FDIV Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdiv_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FDIV Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdivq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_f64(v64 a0, v64 a1, v64 a2)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_f64(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_s8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_s16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_s32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_u8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_u16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_u32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_f64(v64 a0, v64 a1, v64 a2)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_f64(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_s8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_s16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_s32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_u8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_u16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_u32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMADD Dd,Dn,Dm,Da
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfma_f64(v64 a0, v64 a1, v64 a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_f64(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfma_lane_f32(v64 a0, v64 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_lane_f32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
[BurstTargetCpu(BurstTargetCpu.ARMV8A_AARCH64)]
public static v64 vfma_lane_f64(v64 a0, v64 a1, v64 a2, Int32 a3)
{
return vfma_f64(a0, a1, a2);
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_lane_f64(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]
/// Single a0
/// Single a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Single
[DebuggerStepThrough]
public static Single vfmas_lane_f32(Single a0, Single a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
/// Double a0
/// Double a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
[BurstTargetCpu(BurstTargetCpu.ARMV8A_AARCH64)]
public static Double vfmad_lane_f64(Double a0, Double a1, v64 a2, Int32 a3)
{
return vfma_f64(new v64(a0), new v64(a1), a2).Double0;
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfma_laneq_f32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_laneq_f32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfma_laneq_f64(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_laneq_f64(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Sd,Sn,Vm.S[lane]
/// Single a0
/// Single a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Single
[DebuggerStepThrough]
public static Single vfmas_laneq_f32(Single a0, Single a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Dd,Dn,Vm.D[lane]
/// Double a0
/// Double a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vfmad_laneq_f64(Double a0, Double a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMSUB Dd,Dn,Dm,Da
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_f64(v64 a0, v64 a1, v64 a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_f64(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_lane_f32(v64 a0, v64 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_lane_f32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
[BurstTargetCpu(BurstTargetCpu.ARMV8A_AARCH64)]
public static v64 vfms_lane_f64(v64 a0, v64 a1, v64 a2, Int32 a3)
{
return vfms_f64(a0, a1, a2);
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_lane_f64(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]
/// Single a0
/// Single a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Single
[DebuggerStepThrough]
public static Single vfmss_lane_f32(Single a0, Single a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
/// Double a0
/// Double a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
[BurstTargetCpu(BurstTargetCpu.ARMV8A_AARCH64)]
public static Double vfmsd_lane_f64(Double a0, Double a1, v64 a2, Int32 a3)
{
return vfms_f64(new v64(a0), new v64(a1), a2).Double0;
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_laneq_f32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_laneq_f32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_laneq_f64(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_laneq_f64(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Sd,Sn,Vm.S[lane]
/// Single a0
/// Single a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Single
[DebuggerStepThrough]
public static Single vfmss_laneq_f32(Single a0, Single a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]
/// Double a0
/// Double a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vfmsd_laneq_f64(Double a0, Double a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqdmulhh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmulhs_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqrdmulhh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqrdmulhs_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Sd,Hn,Hm
/// Int32 a0
/// Int16 a1
/// Int16 a2
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlalh_s16(Int32 a0, Int16 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Dd,Sn,Sm
/// Int64 a0
/// Int32 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlals_s32(Int64 a0, Int32 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_s16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_s32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Sd,Hn,Hm
/// Int32 a0
/// Int16 a1
/// Int16 a2
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlslh_s16(Int32 a0, Int16 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Dd,Sn,Sm
/// Int64 a0
/// Int32 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlsls_s32(Int64 a0, Int32 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_s16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_s32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Sd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmullh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Dd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmulls_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSUB Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsub_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSUB Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUB Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vsubd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUB Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vsubd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.The USUBL instruction extracts each source vector from the lower half of each source register, while the USUBL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubl_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBW2 Vd.8H,Vn.8H,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBW2 Vd.4S,Vn.4S,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSUBW2 Vd.2D,Vn.2D,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBW2 Vd.8H,Vn.8H,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBW2 Vd.4S,Vn.4S,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register.The USUBW instruction extracts vector elements from the lower half of the first source register, while the USUBW2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USUBW2 Vd.2D,Vn.2D,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubw_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSUB Bd,Bn,Bm
/// SByte a0
/// SByte a1
/// SByte
[DebuggerStepThrough]
public static SByte vqsubb_s8(SByte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSUB Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqsubh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSUB Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqsubs_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSUB Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqsubd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSUB Bd,Bn,Bm
/// Byte a0
/// Byte a1
/// Byte
[DebuggerStepThrough]
public static Byte vqsubb_u8(Byte a0, Byte a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSUB Hd,Hn,Hm
/// UInt16 a0
/// UInt16 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqsubh_u16(UInt16 a0, UInt16 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSUB Sd,Sn,Sm
/// UInt32 a0
/// UInt32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqsubs_u32(UInt32 a0, UInt32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSUB Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqsubd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_s16(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_s32(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_s64(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_u16(v64 a0, v128 a1, v128 a2)
{
return vsubhn_high_s16(a0, a1, a2);
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_u32(v64 a0, v128 a1, v128 a2)
{
return vsubhn_high_s32(a0, a1, a2);
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SUBHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsubhn_high_u64(v64 a0, v128 a1, v128 a2)
{
return vsubhn_high_s64(a0, a1, a2);
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_s16(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_s32(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_s64(v64 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.16B,Vn.8H,Vm.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_u16(v64 a0, v128 a1, v128 a2)
{
return vrsubhn_high_s16(a0, a1, a2);
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.8H,Vn.4S,Vm.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_u32(v64 a0, v128 a1, v128 a2)
{
return vrsubhn_high_s32(a0, a1, a2);
}
/// Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.The results are rounded. For truncated results, see SUBHN.The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSUBHN2 Vd.4S,Vn.2D,Vm.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsubhn_high_u64(v64 a0, v128 a1, v128 a2)
{
return vrsubhn_high_s64(a0, a1, a2);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceq_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceq_u64(v64 a0, v64 a1)
{
return vceq_s64(a0, a1);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqq_u64(v128 a0, v128 a1)
{
return vceqq_s64(a0, a1);
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceq_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Sd,Sn,Sm
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vceqs_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Dd,Dn,Dm
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_u8(v64 a0)
{
return vceqz_s8(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_u8(v128 a0)
{
return vceqzq_s8(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_u16(v64 a0)
{
return vceqz_s16(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_u16(v128 a0)
{
return vceqzq_s16(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_u32(v64 a0)
{
return vceqz_s32(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_u32(v128 a0)
{
return vceqzq_s32(a0);
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_u64(v64 a0)
{
return vceqz_s64(a0);
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_u64(v128 a0)
{
return vceqzq_s64(a0);
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vceqz_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vceqzq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,#0
/// Int64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqzd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Compare bitwise Equal (vector). This instruction compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMEQ Dd,Dn,#0
/// UInt64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqzd_u64(UInt64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Sd,Sn,#0
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vceqzs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMEQ Dd,Dn,#0
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vceqzd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcge_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgeq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcge_u64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgeq_u64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcge_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgeq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcged_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcged_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Sd,Sn,Sm
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcges_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dn,Dm
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcged_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgez_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgezq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dn,#0
/// Int64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgezd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Sd,Sn,#0
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcgezs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dn,#0
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgezd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcle_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcleq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcle_u64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcleq_u64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcle_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcleq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGE Dd,Dm,Dn
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcled_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHS Dd,Dm,Dn
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcled_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Sd,Sm,Sn
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcles_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGE Dd,Dm,Dn
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcled_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLE Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLE Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclez_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLE Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vclezq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLE Dd,Dn,#0
/// Int64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vclezd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLE Sd,Sn,#0
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vclezs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLE Dd,Dn,#0
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vclezd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgt_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgt_u64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtq_u64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgt_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgtd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgtd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Sd,Sn,Sm
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcgts_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dn,Dm
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgtd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcgtz_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcgtzq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Greater than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dn,#0
/// Int64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgtzd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Sd,Sn,#0
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcgtzs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dn,#0
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcgtzd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclt_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclt_u64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltq_u64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vclt_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMGT Dd,Dm,Dn
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcltd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare unsigned Lower (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is less than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMHI Dd,Dm,Dn
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcltd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Sd,Sm,Sn
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vclts_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than (vector). This instruction reads each floating-point value in the first source SIMD&FP register and if the value is less than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMGT Dd,Dm,Dn
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcltd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.8B,Vn.8B,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.16B,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.4H,Vn.4H,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.8H,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Vd.2S,Vn.2S,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Vd.4S,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Dd,Dn,#0
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcltz_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Vd.2D,Vn.2D,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcltzq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMLT Dd,Dn,#0
/// Int64 a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcltzd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Sd,Sn,#0
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcltzs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCMLT Dd,Dn,#0
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcltzd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcage_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcageq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Sd,Sn,Sm
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcages_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Dd,Dn,Dm
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcaged_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcale_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Vd.2D,Vm.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcaleq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Sd,Sm,Sn
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcales_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGE Dd,Dm,Dn
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcaled_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcagt_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcagtq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Sd,Sn,Sm
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcagts_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Dd,Dn,Dm
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcagtd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Dd,Dm,Dn
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcalt_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcaltq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Sd,Sm,Sn
/// Single a0
/// Single a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcalts_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Compare Less than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is less than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FACGT Dd,Dm,Dn
/// Double a0
/// Double a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcaltd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtst_s64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtstq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtst_u64(v64 a0, v64 a1)
{
return vtst_s64(a0, a1);
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtstq_u64(v128 a0, v128 a1)
{
return vtstq_s64(a0, a1);
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vtstd_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: CMTST Dd,Dn,Dm
/// UInt64 a0
/// UInt64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vtstd_u64(UInt64 a0, UInt64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABD Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vabd_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABD Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABD Sd,Sn,Sm
/// Single a0
/// Single a1
/// Single
[DebuggerStepThrough]
public static Single vabds_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABD Dd,Dn,Dm
/// Double a0
/// Double a1
/// Double
[DebuggerStepThrough]
public static Double vabdd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABDL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABDL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABDL instruction writes the vector to the lower half of the destination register and clears the upper half, while the SABDL2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABDL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABDL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABDL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABDL instruction extracts each source vector from the lower half of each source register, while the UABDL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABDL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabdl_high_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABAL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_s8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABAL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_s16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The SABAL instruction extracts each source vector from the lower half of each source register, while the SABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SABAL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_s32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABAL2 Vd.8H,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_u8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABAL2 Vd.4S,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_u16(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.The UABAL instruction extracts each source vector from the lower half of each source register, while the UABAL2 instruction extracts each source vector from the upper half of each source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UABAL2 Vd.2D,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabal_high_u32(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAX Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmax_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAX Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmaxq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMIN Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmin_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMIN Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vminq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNM Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmaxnm_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNM Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmaxnmq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNM Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmaxnm_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNM Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmaxnmq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNM Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vminnm_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNM Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vminnmq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNM Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vminnm_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNM Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vminnmq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHL Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vshld_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHL Dd,Dn,Dm
/// UInt64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vshld_u64(UInt64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Bd,Bn,Bm
/// SByte a0
/// SByte a1
/// SByte
[DebuggerStepThrough]
public static SByte vqshlb_s8(SByte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqshlh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqshls_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqshld_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Bd,Bn,Bm
/// Byte a0
/// SByte a1
/// Byte
[DebuggerStepThrough]
public static Byte vqshlb_u8(Byte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Hd,Hn,Hm
/// UInt16 a0
/// Int16 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqshlh_u16(UInt16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Sd,Sn,Sm
/// UInt32 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqshls_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Dd,Dn,Dm
/// UInt64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqshld_u64(UInt64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SRSHL Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vrshld_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: URSHL Dd,Dn,Dm
/// UInt64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vrshld_u64(UInt64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHL Bd,Bn,Bm
/// SByte a0
/// SByte a1
/// SByte
[DebuggerStepThrough]
public static SByte vqrshlb_s8(SByte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHL Hd,Hn,Hm
/// Int16 a0
/// Int16 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqrshlh_s16(Int16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHL Sd,Sn,Sm
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqrshls_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHL Dd,Dn,Dm
/// Int64 a0
/// Int64 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqrshld_s64(Int64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHL Bd,Bn,Bm
/// Byte a0
/// SByte a1
/// Byte
[DebuggerStepThrough]
public static Byte vqrshlb_u8(Byte a0, SByte a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHL Hd,Hn,Hm
/// UInt16 a0
/// Int16 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqrshlh_u16(UInt16 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHL Sd,Sn,Sm
/// UInt32 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqrshls_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHL Dd,Dn,Dm
/// UInt64 a0
/// Int64 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqrshld_u64(UInt64 a0, Int64 a1)
{
throw new NotImplementedException();
}
/// Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHR Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vshrd_n_s64(Int64 a0, Int32 a1)
{
return a0 >> a1;
}
/// Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHR Dd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vshrd_n_u64(UInt64 a0, Int32 a1)
{
return a0 >> a1;
}
/// Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHL Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vshld_n_s64(Int64 a0, Int32 a1)
{
return a0 << a1;
}
/// Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHL Dd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vshld_n_u64(UInt64 a0, Int32 a1)
{
return a0 << a1;
}
/// Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SRSHR Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vrshrd_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: URSHR Dd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vrshrd_n_u64(UInt64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSRA Dd,Dn,#n
/// Int64 a0
/// Int64 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vsrad_n_s64(Int64 a0, Int64 a1, Int32 a2)
{
return a0 + (a1 >> a2);
}
/// Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USRA Dd,Dn,#n
/// UInt64 a0
/// UInt64 a1
/// Int32 a2
/// UInt64
[DebuggerStepThrough]
public static UInt64 vsrad_n_u64(UInt64 a0, UInt64 a1, Int32 a2)
{
return a0 + (a1 >> a2);
}
/// Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SRSRA Dd,Dn,#n
/// Int64 a0
/// Int64 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vrsrad_n_s64(Int64 a0, Int64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: URSRA Dd,Dn,#n
/// UInt64 a0
/// UInt64 a1
/// Int32 a2
/// UInt64
[DebuggerStepThrough]
public static UInt64 vrsrad_n_u64(UInt64 a0, UInt64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Bd,Bn,#n
/// SByte a0
/// Int32 a1
/// SByte
[DebuggerStepThrough]
public static SByte vqshlb_n_s8(SByte a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Hd,Hn,#n
/// Int16 a0
/// Int32 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqshlh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Sd,Sn,#n
/// Int32 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqshls_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left (immediate). This instruction reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHL Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vqshld_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Bd,Bn,#n
/// Byte a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqshlb_n_u8(Byte a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Hd,Hn,#n
/// UInt16 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqshlh_n_u16(UInt16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Sd,Sn,#n
/// UInt32 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqshls_n_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Left (immediate). This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHL Dd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqshld_n_u64(UInt64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHLU Bd,Bn,#n
/// SByte a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqshlub_n_s8(SByte a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHLU Hd,Hn,#n
/// Int16 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqshluh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHLU Sd,Sn,#n
/// Int32 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqshlus_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHLU Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vqshlud_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshrn_high_n_u64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN Bd,Hn,#n
/// Int16 a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqshrunh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN Hd,Sn,#n
/// Int32 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqshruns_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN Sd,Dn,#n
/// Int64 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqshrund_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrun_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrun_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRUN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrun_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN Bd,Hn,#n
/// Int16 a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqrshrunh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN Hd,Sn,#n
/// Int32 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqrshruns_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN Sd,Dn,#n
/// Int64 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqrshrund_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrun_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrun_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRUN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrun_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN Bd,Hn,#n
/// Int16 a0
/// Int32 a1
/// SByte
[DebuggerStepThrough]
public static SByte vqshrnh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN Hd,Sn,#n
/// Int32 a0
/// Int32 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqshrns_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN Sd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqshrnd_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN Bd,Hn,#n
/// UInt16 a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqshrnh_n_u16(UInt16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN Hd,Sn,#n
/// UInt32 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqshrns_n_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN Sd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqshrnd_n_u64(UInt64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqshrn_high_n_u64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrshrn_high_n_u64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN Bd,Hn,#n
/// Int16 a0
/// Int32 a1
/// SByte
[DebuggerStepThrough]
public static SByte vqrshrnh_n_s16(Int16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN Hd,Sn,#n
/// Int32 a0
/// Int32 a1
/// Int16
[DebuggerStepThrough]
public static Int16 vqrshrns_n_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN Sd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vqrshrnd_n_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN Bd,Hn,#n
/// UInt16 a0
/// Int32 a1
/// Byte
[DebuggerStepThrough]
public static Byte vqrshrnh_n_u16(UInt16 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN Hd,Sn,#n
/// UInt32 a0
/// Int32 a1
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqrshrns_n_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN Sd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqrshrnd_n_u64(UInt64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_s64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN2 Vd.16B,Vn.8H,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN2 Vd.8H,Vn.4S,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQRSHRN2 Vd.4S,Vn.2D,#n
/// 64-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrshrn_high_n_u64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_s8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_s16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_u8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_u16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vshll_high_n_u32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SRI Dd,Dn,#n
/// Int64 a0
/// Int64 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vsrid_n_s64(Int64 a0, Int64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SRI Dd,Dn,#n
/// UInt64 a0
/// UInt64 a1
/// Int32 a2
/// UInt64
[DebuggerStepThrough]
public static UInt64 vsrid_n_u64(UInt64 a0, UInt64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SLI Dd,Dn,#n
/// Int64 a0
/// Int64 a1
/// Int32 a2
/// Int64
[DebuggerStepThrough]
public static Int64 vslid_n_s64(Int64 a0, Int64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SLI Dd,Dn,#n
/// UInt64 a0
/// UInt64 a1
/// Int32 a2
/// UInt64
[DebuggerStepThrough]
public static UInt64 vslid_n_u64(UInt64 a0, UInt64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtn_s32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtnq_s32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtn_u32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtnq_u32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtm_s32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtmq_s32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtm_u32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtmq_u32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtp_s32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtpq_s32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtp_u32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtpq_u32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvta_s32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtaq_s32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvta_u32_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtaq_u32_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Sd,Sn
/// Single a0
/// Int32
[DebuggerStepThrough]
public static Int32 vcvts_s32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Sd,Sn
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvts_u32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Sd,Sn
/// Single a0
/// Int32
[DebuggerStepThrough]
public static Int32 vcvtns_s32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Sd,Sn
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvtns_u32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Sd,Sn
/// Single a0
/// Int32
[DebuggerStepThrough]
public static Int32 vcvtms_s32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Sd,Sn
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvtms_u32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Sd,Sn
/// Single a0
/// Int32
[DebuggerStepThrough]
public static Int32 vcvtps_s32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Sd,Sn
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvtps_u32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Sd,Sn
/// Single a0
/// Int32
[DebuggerStepThrough]
public static Int32 vcvtas_s32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Sd,Sn
/// Single a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvtas_u32_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_s64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_s64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_u64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_u64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtn_s64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtnq_s64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtn_u64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtnq_u64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtm_s64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtmq_s64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtm_u64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtmq_u64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtp_s64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtpq_s64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtp_u64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtpq_u64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvta_s64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtaq_s64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvta_u64_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtaq_u64_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Dd,Dn
/// Double a0
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtd_s64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Dd,Dn
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtd_u64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNS Dd,Dn
/// Double a0
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtnd_s64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTNU Dd,Dn
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtnd_u64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMS Dd,Dn
/// Double a0
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtmd_s64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTMU Dd,Dn
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtmd_u64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPS Dd,Dn
/// Double a0
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtpd_s64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTPU Dd,Dn
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtpd_u64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAS Dd,Dn
/// Double a0
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtad_s64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTAU Dd,Dn
/// Double a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtad_u64_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Sd,Sn,#n
/// Single a0
/// Int32 a1
/// Int32
[DebuggerStepThrough]
public static Int32 vcvts_n_s32_f32(Single a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Sd,Sn,#n
/// Single a0
/// Int32 a1
/// UInt32
[DebuggerStepThrough]
public static UInt32 vcvts_n_u32_f32(Single a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Dd,Dn,#n
/// 64-bit vector a0
/// Int32 a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_n_s64_f64(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Vd.2D,Vn.2D,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_n_s64_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Dd,Dn,#n
/// 64-bit vector a0
/// Int32 a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_n_u64_f64(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Vd.2D,Vn.2D,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_n_u64_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZS Dd,Dn,#n
/// Double a0
/// Int32 a1
/// Int64
[DebuggerStepThrough]
public static Int64 vcvtd_n_s64_f64(Double a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTZU Dd,Dn,#n
/// Double a0
/// Int32 a1
/// UInt64
[DebuggerStepThrough]
public static UInt64 vcvtd_n_u64_f64(Double a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Sd,Sn
/// Int32 a0
/// Single
[DebuggerStepThrough]
public static Single vcvts_f32_s32(Int32 a0)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Sd,Sn
/// UInt32 a0
/// Single
[DebuggerStepThrough]
public static Single vcvts_f32_u32(UInt32 a0)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_f64_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_f64_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_f64_u64(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_f64_u64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Dd,Dn
/// Int64 a0
/// Double
[DebuggerStepThrough]
public static Double vcvtd_f64_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Dd,Dn
/// UInt64 a0
/// Double
[DebuggerStepThrough]
public static Double vcvtd_f64_u64(UInt64 a0)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Sd,Sn,#n
/// Int32 a0
/// Int32 a1
/// Single
[DebuggerStepThrough]
public static Single vcvts_n_f32_s32(Int32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Sd,Sn,#n
/// UInt32 a0
/// Int32 a1
/// Single
[DebuggerStepThrough]
public static Single vcvts_n_f32_u32(UInt32 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Dd,Dn,#n
/// 64-bit vector a0
/// Int32 a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_n_f64_s64(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Vd.2D,Vn.2D,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_n_f64_s64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Dd,Dn,#n
/// 64-bit vector a0
/// Int32 a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_n_f64_u64(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Vd.2D,Vn.2D,#n
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtq_n_f64_u64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SCVTF Dd,Dn,#n
/// Int64 a0
/// Int32 a1
/// Double
[DebuggerStepThrough]
public static Double vcvtd_n_f64_s64(Int64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UCVTF Dd,Dn,#n
/// UInt64 a0
/// Int32 a1
/// Double
[DebuggerStepThrough]
public static Double vcvtd_n_f64_u64(UInt64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.The FCVTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTN Vd.2S,Vn.2D
/// 128-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvt_f32_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.
///
Equivalent instruction: FCVTN2 Vd.4S,Vn.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvt_high_f32_f64(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTL Vd.2D,Vn.2S
/// 64-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvt_f64_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTL2 Vd.2D,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvt_high_f64_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTXN Vd.2S,Vn.2D
/// 128-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcvtx_f32_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTXN Sd,Dn
/// Double a0
/// Single
[DebuggerStepThrough]
public static Single vcvtxd_f32_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.This instruction uses the Round to Odd rounding mode which is not defined by the IEEE 754-2008 standard. This rounding mode ensures that if the result of the conversion is inexact the least significant bit of the mantissa is forced to 1. This rounding mode enables a floating-point value to be converted to a lower precision format via an intermediate precision format while avoiding double rounding errors. For example, a 64-bit floating-point value can be converted to a correctly rounded 16-bit floating-point value by first using this instruction to produce a 32-bit value and then using another instruction with the wanted rounding mode to convert the 32-bit value to the final 16-bit floating-point value.The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half, while the FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FCVTXN2 Vd.4S,Vn.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcvtx_high_f32_f64(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTZ Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrnd_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTZ Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTZ Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrnd_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTZ Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTN Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndn_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTN Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndnq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTN Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndn_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTN Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndnq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTN Sd,Sn
/// Single a0
/// Single
[DebuggerStepThrough]
public static Single vrndns_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTM Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndm_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTM Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndmq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTM Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndm_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTM Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndmq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTP Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndp_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTP Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndpq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTP Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndp_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTP Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndpq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTA Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrnda_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTA Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndaq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTA Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrnda_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTA Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndaq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTI Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndi_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTI Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndiq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTI Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndi_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTI Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndiq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTX Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndx_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTX Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndxq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTX Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrndx_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRINTX Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrndxq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.8H,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.4S,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.The SSHLL instruction extracts vector elements from the lower half of the source register, while the SSHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SSHLL2 Vd.2D,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.8H,Vn.16B,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_u8(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.4S,Vn.8H,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_u16(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: USHLL2 Vd.2D,Vn.4S,#0
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmovl_high_u32(v128 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN Bd,Hn
/// Int16 a0
/// SByte
[DebuggerStepThrough]
public static SByte vqmovnh_s16(Int16 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN Hd,Sn
/// Int32 a0
/// Int16
[DebuggerStepThrough]
public static Int16 vqmovns_s32(Int32 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN Sd,Dn
/// Int64 a0
/// Int32
[DebuggerStepThrough]
public static Int32 vqmovnd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN Bd,Hn
/// UInt16 a0
/// Byte
[DebuggerStepThrough]
public static Byte vqmovnh_u16(UInt16 a0)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN Hd,Sn
/// UInt32 a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqmovns_u32(UInt32 a0)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN Sd,Dn
/// UInt64 a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqmovnd_u64(UInt64 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN2 Vd.16B,Vn.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_s16(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN2 Vd.8H,Vn.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_s32(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTN2 Vd.4S,Vn.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_s64(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN2 Vd.16B,Vn.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_u16(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN2 Vd.8H,Vn.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_u32(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UQXTN2 Vd.4S,Vn.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovn_high_u64(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN Bd,Hn
/// Int16 a0
/// Byte
[DebuggerStepThrough]
public static Byte vqmovunh_s16(Int16 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN Hd,Sn
/// Int32 a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vqmovuns_s32(Int32 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN Sd,Dn
/// Int64 a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vqmovund_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN2 Vd.16B,Vn.8H
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovun_high_s16(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN2 Vd.8H,Vn.4S
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovun_high_s32(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQXTUN2 Vd.4S,Vn.2D
/// 64-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqmovun_high_s64(v64 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_laneq_s16(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_laneq_s32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_laneq_u16(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_laneq_u16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_laneq_u32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLA Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_laneq_u32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmla_laneq_f32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlaq_laneq_f32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_lane_u16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_lane_u32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_laneq_s16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_laneq_s32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_laneq_u16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_laneq_u32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_laneq_u16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_laneq_u32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]
/// Int32 a0
/// Int16 a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlalh_lane_s16(Int32 a0, Int16 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]
/// Int64 a0
/// Int32 a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlals_lane_s32(Int64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_laneq_s16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_laneq_s32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Sd,Hn,Vm.H[lane]
/// Int32 a0
/// Int16 a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlalh_laneq_s16(Int32 a0, Int16 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL Dd,Sn,Vm.S[lane]
/// Int64 a0
/// Int32 a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlals_laneq_s32(Int64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_laneq_s16(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_laneq_s32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_laneq_u16(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_laneq_u16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_laneq_u32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MLS Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_laneq_u32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
/// 64-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmls_laneq_f32(v64 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
///
///
Equivalent instruction: RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsq_laneq_f32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_lane_u16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_lane_u32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_laneq_s16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_laneq_s32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_laneq_u16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_laneq_u32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_laneq_u16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_laneq_u32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]
/// Int32 a0
/// Int16 a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlslh_lane_s16(Int32 a0, Int16 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]
/// Int64 a0
/// Int32 a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlsls_lane_s32(Int64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_laneq_s16(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_laneq_s32(v128 a0, v64 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Sd,Hn,Vm.H[lane]
/// Int32 a0
/// Int16 a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmlslh_laneq_s16(Int32 a0, Int16 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL Dd,Sn,Vm.S[lane]
/// Int64 a0
/// Int32 a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmlsls_laneq_s32(Int64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Vm.D[0]
/// 64-bit vector a0
/// Double a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_n_f64(v64 a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[0]
/// 128-bit vector a0
/// Double a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_n_f64(v128 a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
[BurstTargetCpu(BurstTargetCpu.ARMV8A_AARCH64)]
public static v64 vmul_lane_f64(v64 a0, v64 a1, Int32 a2)
{
return vmul_f64(a0, a1);
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_lane_f64(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]
/// Single a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Single
[DebuggerStepThrough]
public static Single vmuls_lane_f32(Single a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Vm.S[lane]
/// Double a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
public static Double vmuld_lane_f64(Double a0, v64 a1, Int32 a2)
{
return a0 * a1.Double0;
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_s16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_u16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MUL Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_u32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_f32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_f32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vmul_laneq_f64(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Vd.2D,Vn.2D,Vm.D[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmulq_laneq_f64(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Sd,Sn,Vm.S[lane]
/// Single a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Single
[DebuggerStepThrough]
public static Single vmuls_laneq_f32(Single a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMUL Dd,Dn,Vm.D[lane]
/// Double a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vmuld_laneq_f64(Double a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// Int16 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_n_s16(v128 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_n_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// UInt16 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_n_u16(v128 a0, UInt16 a1)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// UInt32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_n_u32(v128 a0, UInt32 a1)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_lane_s16(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_lane_s32(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_lane_u16(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_lane_u32(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_laneq_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL Vd.2D,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_laneq_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL Vd.4S,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_laneq_u16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL Vd.2D,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_laneq_u32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_laneq_s16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_laneq_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_laneq_u16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMULL instruction extracts vector elements from the lower half of the first source register, while the UMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmull_high_laneq_u32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// Int16 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_n_s16(v128 a0, Int16 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// Int32 a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_n_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]
/// Int16 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmullh_lane_s16(Int16 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]
/// Int32 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmulls_lane_s32(Int32 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_lane_s16(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_lane_s32(v128 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_laneq_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_laneq_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Sd,Hn,Vm.H[lane]
/// Int16 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmullh_laneq_s16(Int16 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL Dd,Sn,Vm.S[lane]
/// Int32 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int64
[DebuggerStepThrough]
public static Int64 vqdmulls_laneq_s32(Int32 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_laneq_s16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmull_high_laneq_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]
/// Int16 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int16
[DebuggerStepThrough]
public static Int16 vqdmulhh_lane_s16(Int16 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]
/// Int32 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmulhs_lane_s32(Int32 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqdmulh_laneq_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmulhq_laneq_s16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqdmulh_laneq_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmulhq_laneq_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Hd,Hn,Vm.H[lane]
/// Int16 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// Int16
[DebuggerStepThrough]
public static Int16 vqdmulhh_laneq_s16(Int16 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMULH Sd,Sn,Vm.H[lane]
/// Int32 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vqdmulhs_laneq_s32(Int32 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]
/// Int16 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int16
[DebuggerStepThrough]
public static Int16 vqrdmulhh_lane_s16(Int16 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]
/// Int32 a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// Int32
[DebuggerStepThrough]
public static Int32 vqrdmulhs_lane_s32(Int32 a0, v64 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqrdmulh_laneq_s16(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrdmulhq_laneq_s16(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
/// 64-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqrdmulh_laneq_s32(v64 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
/// 128-bit vector a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqrdmulhq_laneq_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Hd,Hn,Vm.H[lane]
/// Int16 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..7]
/// Int16
[DebuggerStepThrough]
public static Int16 vqrdmulhh_laneq_s16(Int16 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQRDMULH Sd,Sn,Vm.S[lane]
/// Int32 a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vqrdmulhs_laneq_s32(Int32 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_n_s16(v128 a0, v128 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLAL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_n_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// UInt16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_n_u16(v128 a0, v128 a1, UInt16 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLAL instruction extracts vector elements from the lower half of the first source register, while the UMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLAL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// UInt32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlal_high_n_u32(v128 a0, v128 a1, UInt32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_n_s16(v128 a0, v128 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Add Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLAL instruction extracts vector elements from the lower half of the first source register, while the SQDMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlal_high_n_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_n_s16(v128 a0, v128 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMLSL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_n_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// UInt16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_n_u16(v128 a0, v128 a1, UInt16 a2)
{
throw new NotImplementedException();
}
/// Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMLSL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// UInt32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vmlsl_high_n_u32(v128 a0, v128 a1, UInt32 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int16 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_n_s16(v128 a0, v128 a1, Int16 a2)
{
throw new NotImplementedException();
}
/// Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqdmlsl_high_n_s32(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ABS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vabs_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ABS Dd,Dn
/// Int64 a0
/// Int64
[DebuggerStepThrough]
public static Int64 vabsd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ABS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabsq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vabs_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FABS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vabsq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqabs_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqabsq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Bd,Bn
/// SByte a0
/// SByte
[DebuggerStepThrough]
public static SByte vqabsb_s8(SByte a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Hd,Hn
/// Int16 a0
/// Int16
[DebuggerStepThrough]
public static Int16 vqabsh_s16(Int16 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Sd,Sn
/// Int32 a0
/// Int32
[DebuggerStepThrough]
public static Int32 vqabss_s32(Int32 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQABS Dd,Dn
/// Int64 a0
/// Int64
[DebuggerStepThrough]
public static Int64 vqabsd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: NEG Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vneg_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: NEG Dd,Dn
/// Int64 a0
/// Int64
[DebuggerStepThrough]
public static Int64 vnegd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: NEG Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vnegq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FNEG Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vneg_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FNEG Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vnegq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqneg_s64(v64 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqnegq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Bd,Bn
/// SByte a0
/// SByte
[DebuggerStepThrough]
public static SByte vqnegb_s8(SByte a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Hd,Hn
/// Int16 a0
/// Int16
[DebuggerStepThrough]
public static Int16 vqnegh_s16(Int16 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Sd,Sn
/// Int32 a0
/// Int32
[DebuggerStepThrough]
public static Int32 vqnegs_s32(Int32 a0)
{
throw new NotImplementedException();
}
/// Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SQNEG Dd,Dn
/// Int64 a0
/// Int64
[DebuggerStepThrough]
public static Int64 vqnegd_s64(Int64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPE Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrecpe_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPE Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrecpeq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPE Sd,Sn
/// Single a0
/// Single
[DebuggerStepThrough]
public static Single vrecpes_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPE Dd,Dn
/// Double a0
/// Double
[DebuggerStepThrough]
public static Double vrecped_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPS Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrecps_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPS Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrecpsq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPS Sd,Sn,Sm
/// Single a0
/// Single a1
/// Single
[DebuggerStepThrough]
public static Single vrecpss_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPS Dd,Dn,Dm
/// Double a0
/// Double a1
/// Double
[DebuggerStepThrough]
public static Double vrecpsd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSQRT Vd.2S,Vn.2S
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqrt_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSQRT Vd.4S,Vn.4S
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqrtq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSQRT Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vsqrt_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FSQRT Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsqrtq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTE Dd,Dn
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrsqrte_f64(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTE Vd.2D,Vn.2D
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsqrteq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTE Sd,Sn
/// Single a0
/// Single
[DebuggerStepThrough]
public static Single vrsqrtes_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTE Dd,Dn
/// Double a0
/// Double
[DebuggerStepThrough]
public static Double vrsqrted_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTS Dd,Dn,Dm
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrsqrts_f64(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTS Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrsqrtsq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTS Sd,Sn,Sm
/// Single a0
/// Single a1
/// Single
[DebuggerStepThrough]
public static Single vrsqrtss_f32(Single a0, Single a1)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRSQRTS Dd,Dn,Dm
/// Double a0
/// Double a1
/// Double
[DebuggerStepThrough]
public static Double vrsqrtsd_f64(Double a0, Double a1)
{
throw new NotImplementedException();
}
/// Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: BSL Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vbsl_f64(v64 a0, v64 a1, v64 a2)
{
return vbsl_s8(a0, a1, a2);
}
/// Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: BSL Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vbslq_f64(v128 a0, v128 a1, v128 a2)
{
return vbslq_s8(a0, a1, a2);
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_s8(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_s8(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_s16(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_s16(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_s32(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_s32(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_s64(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
return a2;
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_s64(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_u8(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_u8(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_u16(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_u16(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_u32(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_u32(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_u64(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
return a2;
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_u64(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_f32(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_f32(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_lane_f64(v64 a0, Int32 a1, v64 a2, Int32 a3)
{
return a2;
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_lane_f64(v128 a0, Int32 a1, v64 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..15]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_s8(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..15]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_s8(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_s16(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_s16(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_s32(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_s32(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_s64(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_s64(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..15]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_u8(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.B[lane1],Vn.B[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..15]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_u8(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_u16(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.H[lane1],Vn.H[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_u16(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_u32(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_u32(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_u64(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_u64(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_f32(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.S[lane1],Vn.S[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_f32(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane2]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vcopy_laneq_f64(v64 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: INS Vd.D[lane1],Vn.D[lane2]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector a2
/// Lane index to a2. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vcopyq_laneq_f64(v128 a0, Int32 a1, v128 a2, Int32 a3)
{
throw new NotImplementedException();
}
/// Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RBIT Vd.8B,Vn.8B
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrbit_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RBIT Vd.16B,Vn.16B
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrbitq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RBIT Vd.8B,Vn.8B
/// 64-bit vector a0
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vrbit_u8(v64 a0)
{
return vrbit_s8(a0);
}
/// Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: RBIT Vd.16B,Vn.16B
/// 128-bit vector a0
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vrbitq_u8(v128 a0)
{
return vrbitq_s8(a0);
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_lane_f64(v64 a0, Int32 a1)
{
return a0;
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_lane_f64(v64 a0, Int32 a1)
{
return new v128(a0, a0);
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_s8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_s8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_s16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_s16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_s64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_s64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.8B,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_u8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.16B,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_u8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.4H,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_u16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.8H,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_u16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_u32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_u32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_u64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_u64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_f32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.4S,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_f32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vdup_laneq_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Vd.2D,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vdupq_laneq_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Bd,Vn.B[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// SByte
[DebuggerStepThrough]
public static SByte vdupb_lane_s8(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Hd,Vn.H[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// Int16
[DebuggerStepThrough]
public static Int16 vduph_lane_s16(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// Int32
[DebuggerStepThrough]
public static Int32 vdups_lane_s32(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// Int64
[DebuggerStepThrough]
public static Int64 vdupd_lane_s64(v64 a0, Int32 a1)
{
return a0.SLong0;
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Bd,Vn.B[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// Byte
[DebuggerStepThrough]
public static Byte vdupb_lane_u8(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Hd,Vn.H[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// UInt16
[DebuggerStepThrough]
public static UInt16 vduph_lane_u16(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// UInt32
[DebuggerStepThrough]
public static UInt32 vdups_lane_u32(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// UInt64
[DebuggerStepThrough]
public static UInt64 vdupd_lane_u64(v64 a0, Int32 a1)
{
return a0.ULong0;
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// Single
[DebuggerStepThrough]
public static Single vdups_lane_f32(v64 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
public static Double vdupd_lane_f64(v64 a0, Int32 a1)
{
return a0.Double0;
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Bd,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// SByte
[DebuggerStepThrough]
public static SByte vdupb_laneq_s8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Hd,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// Int16
[DebuggerStepThrough]
public static Int16 vduph_laneq_s16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// Int32
[DebuggerStepThrough]
public static Int32 vdups_laneq_s32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// Int64
[DebuggerStepThrough]
public static Int64 vdupd_laneq_s64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Bd,Vn.B[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..15]
/// Byte
[DebuggerStepThrough]
public static Byte vdupb_laneq_u8(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Hd,Vn.H[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..7]
/// UInt16
[DebuggerStepThrough]
public static UInt16 vduph_laneq_u16(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// UInt32
[DebuggerStepThrough]
public static UInt32 vdups_laneq_u32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// UInt64
[DebuggerStepThrough]
public static UInt64 vdupd_laneq_u64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Sd,Vn.S[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..3]
/// Single
[DebuggerStepThrough]
public static Single vdups_laneq_f32(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vdupd_laneq_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_u8(v128 a0, v128 a1)
{
return vpaddq_s8(a0, a1);
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_u16(v128 a0, v128 a1)
{
return vpaddq_s16(a0, a1);
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_u32(v128 a0, v128 a1)
{
return vpaddq_s32(a0, a1);
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_u64(v128 a0, v128 a1)
{
return vpaddq_s64(a0, a1);
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpaddq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINP Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_u8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINP Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_u16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_u32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vpmaxnm_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxnmq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpmaxnmq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vpminnm_f32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminnmq_f32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vpminnmq_f64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Dd,Vn.2D
/// 128-bit vector a0
/// Int64
[DebuggerStepThrough]
public static Int64 vpaddd_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Dd,Vn.2D
/// 128-bit vector a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vpaddd_u64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vpadds_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vpaddd_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vpmaxs_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vpmaxqd_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vpmins_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vpminqd_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vpmaxnms_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vpmaxnmqd_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vpminnms_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vpminnmqd_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Bd,Vn.8B
/// 64-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vaddv_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Bd,Vn.16B
/// 128-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vaddvq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Hd,Vn.4H
/// 64-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vaddv_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Hd,Vn.8H
/// 128-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vaddvq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vaddv_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Sd,Vn.4S
/// 128-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vaddvq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Dd,Vn.2D
/// 128-bit vector a0
/// Int64
[DebuggerStepThrough]
public static Int64 vaddvq_s64(v128 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Bd,Vn.8B
/// 64-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vaddv_u8(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Bd,Vn.16B
/// 128-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vaddvq_u8(v128 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Hd,Vn.4H
/// 64-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vaddv_u16(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Hd,Vn.8H
/// 128-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vaddvq_u16(v128 a0)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vaddv_u32(v64 a0)
{
throw new NotImplementedException();
}
/// Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDV Sd,Vn.4S
/// 128-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vaddvq_u32(v128 a0)
{
throw new NotImplementedException();
}
/// Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ADDP Dd,Vn.2D
/// 128-bit vector a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vaddvq_u64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vaddv_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Vt.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vaddvq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FADDP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vaddvq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLV Hd,Vn.8B
/// 64-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vaddlv_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLV Hd,Vn.16B
/// 128-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vaddlvq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLV Sd,Vn.4H
/// 64-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vaddlv_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLV Sd,Vn.8H
/// 128-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vaddlvq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLP Vd.1D,Vn.2S
/// 64-bit vector a0
/// Int64
[DebuggerStepThrough]
public static Int64 vaddlv_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SADDLV Dd,Vn.4S
/// 128-bit vector a0
/// Int64
[DebuggerStepThrough]
public static Int64 vaddlvq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLV Hd,Vn.8B
/// 64-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vaddlv_u8(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLV Hd,Vn.16B
/// 128-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vaddlvq_u8(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLV Sd,Vn.4H
/// 64-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vaddlv_u16(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLV Sd,Vn.8H
/// 128-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vaddlvq_u16(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLP Vd.1D,Vn.2S
/// 64-bit vector a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vaddlv_u32(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UADDLV Dd,Vn.4S
/// 128-bit vector a0
/// UInt64
[DebuggerStepThrough]
public static UInt64 vaddlvq_u32(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXV Bd,Vn.8B
/// 64-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vmaxv_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXV Bd,Vn.16B
/// 128-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vmaxvq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXV Hd,Vn.4H
/// 64-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vmaxv_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXV Hd,Vn.8H
/// 128-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vmaxvq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vmaxv_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMAXV Sd,Vn.4S
/// 128-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vmaxvq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXV Bd,Vn.8B
/// 64-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vmaxv_u8(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXV Bd,Vn.16B
/// 128-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vmaxvq_u8(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXV Hd,Vn.4H
/// 64-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vmaxv_u16(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXV Hd,Vn.8H
/// 128-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vmaxvq_u16(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vmaxv_u32(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMAXV Sd,Vn.4S
/// 128-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vmaxvq_u32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vmaxv_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXV Sd,Vn.4S
/// 128-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vmaxvq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vmaxvq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINV Bd,Vn.8B
/// 64-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vminv_s8(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINV Bd,Vn.16B
/// 128-bit vector a0
/// SByte
[DebuggerStepThrough]
public static SByte vminvq_s8(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINV Hd,Vn.4H
/// 64-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vminv_s16(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINV Hd,Vn.8H
/// 128-bit vector a0
/// Int16
[DebuggerStepThrough]
public static Int16 vminvq_s16(v128 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vminv_s32(v64 a0)
{
throw new NotImplementedException();
}
/// Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: SMINV Sd,Vn.4S
/// 128-bit vector a0
/// Int32
[DebuggerStepThrough]
public static Int32 vminvq_s32(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINV Bd,Vn.8B
/// 64-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vminv_u8(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINV Bd,Vn.16B
/// 128-bit vector a0
/// Byte
[DebuggerStepThrough]
public static Byte vminvq_u8(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINV Hd,Vn.4H
/// 64-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vminv_u16(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINV Hd,Vn.8H
/// 128-bit vector a0
/// UInt16
[DebuggerStepThrough]
public static UInt16 vminvq_u16(v128 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINP Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vminv_u32(v64 a0)
{
throw new NotImplementedException();
}
/// Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UMINV Sd,Vn.4S
/// 128-bit vector a0
/// UInt32
[DebuggerStepThrough]
public static UInt32 vminvq_u32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vminv_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINV Sd,Vn.4S
/// 128-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vminvq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vminvq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vmaxnmv_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMAX (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMV Sd,Vn.4S
/// 128-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vmaxnmvq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Maximum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMAXNMP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vmaxnmvq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Sd,Vn.2S
/// 64-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vminnmv_f32(v64 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMIN (scalar).This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMV Sd,Vn.4S
/// 128-bit vector a0
/// Single
[DebuggerStepThrough]
public static Single vminnmvq_f32(v128 a0)
{
throw new NotImplementedException();
}
/// Floating-point Minimum Number of Pair of elements (scalar). This instruction compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMINNMP Dd,Vn.2D
/// 128-bit vector a0
/// Double
[DebuggerStepThrough]
public static Double vminnmvq_f64(v128 a0)
{
throw new NotImplementedException();
}
/// Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
/// 64-bit vector a0
/// 64-bit vector a1
/// Int32 a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vext_f64(v64 a0, v64 a1, Int32 a2)
{
return a0;
}
/// Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
/// 128-bit vector a0
/// 128-bit vector a1
/// Int32 a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vextq_f64(v128 a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_u8(v64 a0, v64 a1)
{
return vzip1_s8(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_u8(v128 a0, v128 a1)
{
return vzip1q_s8(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_u16(v64 a0, v64 a1)
{
return vzip1_s16(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_u16(v128 a0, v128 a1)
{
return vzip1q_s16(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_u32(v64 a0, v64 a1)
{
return vzip1_s32(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_u32(v128 a0, v128 a1)
{
return vzip1q_s32(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_u64(v128 a0, v128 a1)
{
return vzip1q_s64(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip1_f32(v64 a0, v64 a1)
{
return vzip1_s32(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_f32(v128 a0, v128 a1)
{
return vzip1q_s32(a0, a1);
}
/// Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip1q_f64(v128 a0, v128 a1)
{
return vzip1q_s64(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_u8(v64 a0, v64 a1)
{
return vzip2_s8(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_u8(v128 a0, v128 a1)
{
return vzip2q_s8(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_u16(v64 a0, v64 a1)
{
return vzip2_s16(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_u16(v128 a0, v128 a1)
{
return vzip2q_s16(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_u32(v64 a0, v64 a1)
{
return vzip2_s32(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_u32(v128 a0, v128 a1)
{
return vzip2q_s32(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_u64(v128 a0, v128 a1)
{
return vzip2q_s64(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vzip2_f32(v64 a0, v64 a1)
{
return vzip2_s32(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_f32(v128 a0, v128 a1)
{
return vzip2q_s32(a0, a1);
}
/// Zip vectors (secondary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP1 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: ZIP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vzip2q_f64(v128 a0, v128 a1)
{
return vzip2q_s64(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_u8(v64 a0, v64 a1)
{
return vuzp1_s8(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_u8(v128 a0, v128 a1)
{
return vuzp1q_s8(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_u16(v64 a0, v64 a1)
{
return vuzp1_s16(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_u16(v128 a0, v128 a1)
{
return vuzp1q_s16(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_u32(v64 a0, v64 a1)
{
return vuzp1_s32(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_u32(v128 a0, v128 a1)
{
return vuzp1q_s32(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_u64(v128 a0, v128 a1)
{
return vuzp1q_s64(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp1_f32(v64 a0, v64 a1)
{
return vuzp1_s32(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_f32(v128 a0, v128 a1)
{
return vuzp1q_s32(a0, a1);
}
/// Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP2 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp1q_f64(v128 a0, v128 a1)
{
return vuzp1q_s64(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_u8(v64 a0, v64 a1)
{
return vuzp2_s8(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_u8(v128 a0, v128 a1)
{
return vuzp2q_s8(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_u16(v64 a0, v64 a1)
{
return vuzp2_s16(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_u16(v128 a0, v128 a1)
{
return vuzp2q_s16(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_u32(v64 a0, v64 a1)
{
return vuzp2_s32(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_u32(v128 a0, v128 a1)
{
return vuzp2q_s32(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_u64(v128 a0, v128 a1)
{
return vuzp2q_s64(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vuzp2_f32(v64 a0, v64 a1)
{
return vuzp2_s32(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_f32(v128 a0, v128 a1)
{
return vuzp2q_s32(a0, a1);
}
/// Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.This instruction can be used with UZP1 to de-interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: UZP2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vuzp2q_f64(v128 a0, v128 a1)
{
return vuzp2q_s64(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_u8(v64 a0, v64 a1)
{
return vtrn1_s8(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_u8(v128 a0, v128 a1)
{
return vtrn1q_s8(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_u16(v64 a0, v64 a1)
{
return vtrn1_s16(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_u16(v128 a0, v128 a1)
{
return vtrn1q_s16(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_u32(v64 a0, v64 a1)
{
return vtrn1_s32(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_u32(v128 a0, v128 a1)
{
return vtrn1q_s32(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_u64(v128 a0, v128 a1)
{
return vtrn1q_s64(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn1_f32(v64 a0, v64 a1)
{
return vtrn1_s32(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_f32(v128 a0, v128 a1)
{
return vtrn1q_s32(a0, a1);
}
/// Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN2, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN1 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn1q_f64(v128 a0, v128 a1)
{
return vtrn1q_s64(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_s8(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_s16(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_s16(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_s32(v64 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_s32(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_s64(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.8B,Vn.8B,Vm.8B
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_u8(v64 a0, v64 a1)
{
return vtrn2_s8(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.16B,Vn.16B,Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_u8(v128 a0, v128 a1)
{
return vtrn2q_s8(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.4H,Vn.4H,Vm.4H
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_u16(v64 a0, v64 a1)
{
return vtrn2_s16(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.8H,Vn.8H,Vm.8H
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_u16(v128 a0, v128 a1)
{
return vtrn2q_s16(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_u32(v64 a0, v64 a1)
{
return vtrn2_s32(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_u32(v128 a0, v128 a1)
{
return vtrn2q_s32(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_u64(v128 a0, v128 a1)
{
return vtrn2q_s64(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2S,Vn.2S,Vm.2S
/// 64-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vtrn2_f32(v64 a0, v64 a1)
{
return vtrn2_s32(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.4S,Vn.4S,Vm.4S
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_f32(v128 a0, v128 a1)
{
return vtrn2q_s32(a0, a1);
}
/// Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.By using this instruction with TRN1, a 2 x 2 matrix can be transposed.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TRN2 Vd.2D,Vn.2D,Vm.2D
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vtrn2q_f64(v128 a0, v128 a1)
{
return vtrn2q_s64(a0, a1);
}
/// Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
/// 128-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqtbl1_s8(v128 a0, v64 a1)
{
throw new NotImplementedException();
}
/// Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqtbl1q_s8(v128 a0, v128 a1)
{
throw new NotImplementedException();
}
/// Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBL Vd.8B,{Vn.16B},Vm.8B
/// 128-bit vector a0
/// 64-bit vector a1
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqtbl1_u8(v128 a0, v64 a1)
{
return vqtbl1_s8(a0, a1);
}
/// Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBL Vd.16B,{Vn.16B},Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqtbl1q_u8(v128 a0, v128 a1)
{
return vqtbl1q_s8(a0, a1);
}
/// Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B
/// 64-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqtbx1_s8(v64 a0, v128 a1, v64 a2)
{
throw new NotImplementedException();
}
/// Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqtbx1q_s8(v128 a0, v128 a1, v128 a2)
{
throw new NotImplementedException();
}
/// Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBX Vd.8B,{Vn.16B},Vm.8B
/// 64-bit vector a0
/// 128-bit vector a1
/// 64-bit vector a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vqtbx1_u8(v64 a0, v128 a1, v64 a2)
{
return vqtbx1_s8(a0, a1, a2);
}
/// Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: TBX Vd.16B,{Vn.16B},Vm.16B
/// 128-bit vector a0
/// 128-bit vector a1
/// 128-bit vector a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vqtbx1q_u8(v128 a0, v128 a1, v128 a2)
{
return vqtbx1q_s8(a0, a1, a2);
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 64-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..0]
/// Double
[DebuggerStepThrough]
public static Double vget_lane_f64(v64 a0, Int32 a1)
{
return a0.Double0;
}
/// Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: DUP Dd,Vn.D[lane]
/// 128-bit vector a0
/// Lane index to a0. Must be an immediate in the range of [0..1]
/// Double
[DebuggerStepThrough]
public static Double vgetq_lane_f64(v128 a0, Int32 a1)
{
throw new NotImplementedException();
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MOV Vd.D[lane],Rn
/// Double a0
/// 64-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..0]
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vset_lane_f64(Double a0, v64 a1, Int32 a2)
{
return new v64(a0);
}
/// Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: MOV Vd.D[lane],Rn
/// Double a0
/// 128-bit vector a1
/// Lane index to a1. Must be an immediate in the range of [0..1]
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vsetq_lane_f64(Double a0, v128 a1, Int32 a2)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPX Sd,Sn
/// Single a0
/// Single
[DebuggerStepThrough]
public static Single vrecpxs_f32(Single a0)
{
throw new NotImplementedException();
}
/// Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FRECPX Dd,Dn
/// Double a0
/// Double
[DebuggerStepThrough]
public static Double vrecpxd_f64(Double a0)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2S,Vn.2S,Vm.S[0]
/// 64-bit vector a0
/// 64-bit vector a1
/// Single a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_n_f32(v64 a0, v64 a1, Single a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.4S,Vn.4S,Vm.S[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Single a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_n_f32(v128 a0, v128 a1, Single a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMADD Dd,Dn,Dm,Da
/// 64-bit vector a0
/// 64-bit vector a1
/// Double a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfma_n_f64(v64 a0, v64 a1, Double a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLA Vd.2D,Vn.2D,Vm.D[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Double a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmaq_n_f64(v128 a0, v128 a1, Double a2)
{
throw new NotImplementedException();
}
/// Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMSUB Dd,Dn,Dm,Da
/// 64-bit vector a0
/// 64-bit vector a1
/// Double a2
/// 64-bit vector
[DebuggerStepThrough]
public static v64 vfms_n_f64(v64 a0, v64 a1, Double a2)
{
throw new NotImplementedException();
}
/// Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
///
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[0]
/// 128-bit vector a0
/// 128-bit vector a1
/// Double a2
/// 128-bit vector
[DebuggerStepThrough]
public static v128 vfmsq_n_f64(v128 a0, v128 a1, Double a2)
{
throw new NotImplementedException();
}
}
}
}